1. Field of the Invention
The present invention generally relates to protection circuitry for integrated circuits. More particularly, the present invention relates to an ESD protection circuit suitable for an integrated circuit with input voltages beyond power supply voltage range.
2. Description of the Related Art
In sub-micron CMOS integrated circuits (ICs), is electrostatic discharge, ESD hereinafter, is a reliability concern. Referring to FIG. 1, a conventional ESD protection circuit fabricated onto a semiconductor substrate is schematically illustrated in a cross-sectional view. The fabricated ESD protection circuit is a lateral semiconductor controlled rectifier. In the drawing, reference numeral 1 designates a core circuit or an internal circuit for an integrated circuit, the core circuit 1 being powered by voltage sources VSS and VDD while operating. Reference numeral 2 represents a bonding pad to which the lateral semiconductor controlled rectifier 3 is electrically connected. During an ESD event, the lateral semiconductor controlled rectifier 3 can turn on to bypass the ESD stress occurring at the bonding pad and thus protect the core circuit 1 from ESD damage.
As shown in FIG. 1, an n-well 11 is formed on a p-type semiconductor substrate 10. A p+ doped region 12 is formed in the n-well 11 as an anode of the lateral semiconductor controlled rectifier 3, while an n+ doped region 13 is formed in the p-type substrate 10 as a cathode of the lateral semiconductor controlled rectifier 3. Moreover, an n+ contact region 14 and a p+ contact region 15 are formed in the n-well 11 and the p-type substrate 10, respectively.
The lateral semiconductor controlled rectifier 3 can be considered as two bipolar transistors T1 and T2. As shown in FIG. 1, the pnp transistor T1 is formed by the anode (p+ doped region 12) as an emitter, the n-well 11 as a base, and the p-type substrate 10 as a collector. The npn transistor T2 is formed by the cathode (n+ doped region 13) as an emitter, the p-type substrate 10 as a base, and the n-well 11 as a collector. Moreover, Rwell and Rsub denote the spreading resistances of the n-well 11 and the p-type substrate 10, respectively. In FIG. 1, the p+ doped region 12 and the n+ contact region 14 are tied together to the bonding pad 2, the n+ doped region 13 and the p+ contact region 15 are tied together to VSS, which is grounded under circuit operation.
When ESD stress occurs to the bonding pad 2, the VSS and VDD are not powered, that is, the nodes is floating. If the ESD stress is relatively positive to VSS the junction between the n-well 11 and p-type substrate 10 enters avalanche breakdown to trigger the lateral semiconductor controlled rectifier 3, where the trigger voltage and the trigger current are denoted by Vtrig and Itrig, respectively. Therefore, the lateral semiconductor controlled rectifier 3 turns on to conduct a current bypassing the ESD stress, and thus clamp the potential between the anode 12 and the cathode 13 at a holding voltage Vh so as to protect the core circuit 1 from ESD damage. If the ESD stress is relatively negative to VSS, the junction between the n-well 11 and p-type substrate 10 is forward-biased to protect the core circuit 1 from ESD damage as well. The I-V characteristic curve of the lateral semiconductor controlled rectifier 3 is shown in FIG. 2.
However, some specific integrated circuits are provided with I/O pins having operational voltages that exceed the range between VSS and VDD under circuit operation. In other words, there are some signals having a potential greater than VDD or less than VSS. However, when the signal with a potential lower s than VSS is provided, the junction between the n-well 11 and the p-type substrate 10 will be forward-biased so that the performance of the core circuit 1 is affected.
Therefore, it is an object of the present invention to provide an ESD protection circuit for an integrated circuit with operating voltages exceeding power supply voltages, which can be turned off under circuit operation without disturbing circuit performance.
For achieving the above-identified object, the present invention provides an ESD protection circuit having a semiconductor controlled rectifier and an MOS transistor. The semiconductor is controlled rectifier has an anode and a cathode connected to a first circuit node and a second circuit node, respectively. The MOS transistor is connected between the anode and an anode gate of the semiconductor controlled rectifier to increase the magnitude of a turn-on voltage at which the semiconductor controlled rectifier enters a negative forward bias.
Moreover, the present invention provides an ESD protection circuit comprising a p-type semiconductor layer having a first contact region, an n-type semiconductor layer having a second contact region, an MOS transistor, and an n-type doped region. The n-type semiconductor layer is in contact with the p-type semiconductor layer to establish a junction therebetween. The MOS transistor is formed in the n-type semiconductor layer with one source/drain region connected to a first circuit node and another source/drain region connected to the second contact region. The n-type doped region is formed in the p-type semiconductor layer and connected with the first contact region to a second circuit node.
Accordingly, the ESD protection of the present invention can be used on those I/O pins having operational voltages that greater than VDD or even less than VSS to ensure that the MOS transistor can turn off under circuit operation without disturbing circuit performance. During an ESD event, the potential between the first and second circuit nodes can still be clamped by the semiconductor controlled rectifier to a low voltage so as to protect a core circuit of an integrated circuit from ESD damage.